Lesson about the architecture of the CPU. Contains elements of component 1.1.1 (Fetch, Decode, Execute cycle, CPU components such as ALU,Control Unit, Registers) and Von Neumann Architecture) from OCR GCSE Computer Science spec (J277).
Contains explanations of the fetch, decode, execute cycle with a step by step diagram showing how data is received from RAM, goes through registers and then executed. Tasks provided in the Powerpoint for students to complete to promote independent learning. Notes also provided to expand on points for students/teacher.
Included is a Powerpoint with notes and tasks to help aid progress.
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Excellent resource. I particularly like the fetch-execute cycle explanation. Thank you.
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